1. Field of the Invention
The present invention relates to a stacked semiconductor package, and a fabricating method thereof.
2. Background of the Related Art
FIGS. 1A through 1D illustrate an example of a background art method of forming stacked semiconductor packages. FIG. 1A shows a cross-sectional view of an upper thin small outline (TSO) package 1 and a lower TSO package 2, each TSO package being fabricated by packaging two semiconductor chips with a molding resin. Outer leads 3 are formed on outer ends of each TSO package 1, 2. Those TSO packages 1, 2 can be distinguished by the shape of their outer leads 3. As a result of a stacking process, a plurality of leads 3 are formed on opposite sides of the upper and lower TSO packages 1, 2.
FIG. 1B shows the upper TSO package 1 stacked to an upper side of the lower TSO package 2. A nipper 4 picks up the stacked TSO packages 1, 2, as shown in FIG. 1C, and the leads 3 are dipped in a solder solution 5 in a vessel 6 such that a connecting portion of the outer leads 3 of the stacked TSO packages 1, 2 is covered with the solder solution 5. The solder solution 5 is heated to its boiling point at approximately 250xc2x0 C. To prevent the plurality of outer leads 3 from inadvertently contacting one another, each outer lead is soldered separately. During the soldering process, the outer leads 3 of the TSO packages 1, 2 are dipped in the solder solution 5 or smeared with drops splashed from the boiling solder solution 5. The stacked TSO package is completed once the solder solution at the outer leads 3 of the upper and lower TSO packages 1, 2 is made to reflow, as illustrated in FIG. 1D.
The background art method has various disadvantages. It is difficult to control the amount of solder solution which contacts the stacked TSO package, because the outer leads are dipped in the solder solution or smeared with the drops splashed from the boiling solder solution. In addition, when a plurality of the outer leads are densely packed together, it is more difficult to separately dip each outer lead in the solder solution, and short-circuiting can result when adjacent outer leads are connected to one another by the solder solution.
It is an object of the present invention to provide a method of forming a stacked semiconductor package, similar in size to a semiconductor chip, which is easier to perform than background art methods.
It is also an object of the present invention to provide a method of forming a stacked semiconductor package which can prevent short-circuiting that can occur when terminals are inadvertently connected to one another.
A stacked semiconductor package embodying the present invention includes first and second semiconductor chips having first sides, wherein a plurality of chip pads are formed on the first sides of the chips, and a bonding tape is adhered to the first and second chips, the bonding tape having conductive interconnections that couple corresponding chip pads of the first and second semiconductor chips. A package embodying the invention may also include a plurality of conductive media which are used to couple the chip pads to external devices. A package embodying the invention may be configured such that the first sides of the chips are substantially parallel to one another with the first sides being arranged on either the external sides of the package, or so that they face one another inside the package. A heat conducting plate may also be connected between the first and second chips.
A device embodying the invention may also comprise a bonding tape for joining two semiconductor chips. The bonding tape would include a flexible adhesive layer configured so that it can be adhered to first surfaces of first and second semiconductor chips to attach the chips to each other. The bonding tape would also include a plurality of conductive regions formed on the adhesive layer such that when the adhesive layer is adhered to the first and second semiconductor chips, the conductive regions will electrically couple chip pads on the first semiconductor chip to corresponding chip pads on the second semiconductor chip.
A method embodying the invention includes the steps of attaching a first semiconductor chip to a second semiconductor chip using a bonding tape that adheres to first surfaces of the chips, wherein conductive interconnections on the bonding tape also electrically couple corresponding chip pads formed on the chips. The method also includes bending the bonding tape such that the first surfaces of the first and second semiconductor chips are arranged substantially parallel to one another. A method of bonding the invention can also include a step of attaching a plurality of conductive media to the conductive interconnections on the bonding tape such that the plurality of conductive media can serve as external leads of the package.
An alternative method of forming a stacked semiconductor package, embodying the invention, includes a first step of sawing a wafer on which a plurality of semiconductor chips are arranged in pairs to separate the wafer into a plurality of chips; adhering a bonding tape to the chips so that the bonding tape attaches adjacent pairs of chips to one another, and so that conductive interconnections on the bonding tape electrically connect respective chip pads of adjacent pairs of the chips; cutting the bonding tape; and stacking the pairs of semiconductor chips so that they face each other. Some methods embodying the invention may include an additional step of adhering conductive media to the bonding tape. Also, the wafer may be attached to an adhesive mounting foil before the wafer is cut into individual chips.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.